1. The Field of the Invention
The present invention relates to microelectronic device packaging. More particularly, the present invention relates to achieving a ball array and trace layout that enhances signal processing with the packaged microelectronic device. In particular, the present invention relates to a ball array and trace layout electrical enhancement technique that achieves a preferred difference in capacitance between any two ball pad sites and their respective traces for a printed circuit board ball array.
2. The Relevant Technology
In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures which includes active or operable portions of semiconductor devices. In the context of this document, the term "semiconductive substrate" is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term substrate refers to any supporting structure including but not limited to the semiconductive substrates described above.
As device operating speeds and the slew rates of driver switching simultaneously increase, the quality of the power V.sub.CC and ground V.sub.SS routing systems become a critical factor in the overall integrity of the system. In current designs, providing a source of charge in close vicinity of the switching activity is essential for the proper functioning of an overall integrated circuit system.
Prior art systems have been able to somewhat improve electrical performance with discrete capacitive components. These discrete capacitive components are usually mounted on a package substrate and then directly interconnected to the power V.sub.cc and ground V.sub.ss through conductive leads and vias. However, a major problem with using discrete capacitive components to decouple the power V.sub.cc and ground V.sub.ss traces is that they lose their effectiveness at high frequencies. Furthermore, there is often not enough space on the semiconductor package surface to mount a larger number of discrete capacitative components that may be necessary to decouple the system.
Although it is a common practice to add ground shielding around signal traces in order to reduce cross-talk between electrically conductive traces that communicate with an electronic device, ground traces themselves can induce cross-talk with adjacent signal traces. Another practice is to remove all excess metal between signal traces that is not being used for ground shielding. The placement of ground traces between signal traces increases the amount of real estate that is required upon a given substrate such as a printed circuit board (PCB). Another problem that exists is that signal traces can be configured in a given ball pad column that includes a ball array and signal traces that are configured into a different ball pad column in the ball array. These configurations lend themselves to an increased capacitance difference between any given ball pad and its respective trace and any other ball pad and its respective trace.
A phenomenon that occurs during overmolding of an integrated circuit chip package is flashing of encapsulation material between a substrate and a mold half. The often irregular wiring layout that may be the result of auto routing or hand routing of traces between bond wire pads in a bond wire pad column, and ball pads in a ball pad column, may cause some spacing between traces to be large enough to allow flashing of encapsulation material.
What is needed in the art is a ball array and trace layout electrical enhancement technique that overcomes the foregoing problems of prior art.